Capability

Semiconductor assembly and test in Singapore

Semiconductor assembly and test packages fabricated dies into finished devices — die attach, wire bonding or flip-chip, encapsulation and lead finishing — then verifies function through wafer probe and final test. Buyers evaluate package types, test coverage, throughput and quality certification.

Evaluating a back-end OSAT (outsourced semiconductor assembly and test) or IDM back-end line starts with packaging breadth: how far a supplier can carry a die from the simplest wire-bond leadframe and laminate packages, through flip-chip and wafer-level packaging (WLP/WLCSP) and fan-out (FOWLP), up to 2.5D/3D advanced packaging — silicon interposers, chiplet integration, and high-bandwidth memory (HBM) stacks. The second axis is test depth: wafer probe / wafer sort before dicing, final test after packaging, and burn-in for reliability screening, backed by in-house test-program development. Buyers then weigh throughput and yield at volume, and the quality system — IATF 16949 for automotive, AEC-Q device qualification, and the traceability that lets a customer stand behind a shipped part.

Singapore is one of Asia's densest back-end hubs: independent OSATs, IDM back-end lines run by the device makers themselves, and — most visibly since 2024 — a wave of advanced-packaging investment chasing AI and high-performance computing. The established base sits in Yishun, Ang Mo Kio, Serangoon, Woodlands and Toa Payoh; the new advanced-packaging frontier — panel-level chiplet integration and HBM stacking — is landing in Tampines and Micron's North Coast corridor. The shift is from commodity wire-bond toward heterogeneous integration, where the package, not the transistor, is increasingly where performance is won.

Also known as: OSAT · outsourced semiconductor assembly and test · IC packaging and test · back-end assembly · wafer test · chip packaging · assembly and test

Capability specifications

Assembly steps: die attach, wire bonding, flip-chip, moulding, singulation
Package types: QFN, BGA, QFP, WLCSP, SiP
Test stages: wafer probe (sort), final test, burn-in
Standards: JEDEC package and reliability standards
Certifications: ISO 9001, IATF 16949

Companies with this capability in Singapore

STATS ChipPAC
A Singapore-headquartered independent OSAT and back-end manufacturer, owned by China's JCET Group. Its two Yishun sites cover package design, wafer bumping, flip-chip, wafer-level and SiP packaging and 2.5D/3D advanced packaging, plus wafer probe and final test. Among the largest operating back-end footprints in Singapore.
Website (opens STATS ChipPAC in a new tab)
UTAC (United Test and Assembly Center)
A Singapore-headquartered independent OSAT with multiple Ang Mo Kio and Serangoon plants. Packaging spans leadframe, laminate, MEMS and sensors, image sensors, SiP, WLCSP and bumping, and power; test covers wafer sort, final test and market-specific test across automotive, communications, computing, consumer and industrial.
Website (opens UTAC (United Test and Assembly Center) in a new tab)
Micron Technology (Singapore)
An integrated device manufacturer running one of Micron's two global 3D NAND flash memory hubs, at the North Coast Wafer Fab Park — 300mm fabs (Fab 10A, Fab 10X) with roughly 500,000 sq ft of cleanroom each, and Fab 10B under construction to expand NAND capacity for AI and data-centre storage. It has also broken ground on a new HBM advanced-packaging facility nearby — a roughly US$7 billion investment for high-bandwidth-memory packaging, assembly and test, slated to begin from 2026.
Website (opens Micron Technology (Singapore) in a new tab)
STMicroelectronics (Singapore)
An integrated device manufacturer running Singapore's first front-end wafer fab, at Ang Mo Kio, and part of ST's largest global front-end footprint (around 4,400 staff across four Singapore sites). It runs front-end fabrication and electrical wafer sort with a focus on MEMS — including a piezoelectric-MEMS Lab-in-Fab R&D line run with A*STAR and ULVAC — alongside packaging R&D. Its Toa Payoh site operates as a design centre and fab back-end handling assembly and test, while Ang Mo Kio runs electrical wafer sort.
Website (opens STMicroelectronics (Singapore) in a new tab)
Infineon (Singapore)
Infineon's Asia-Pacific regional base, at Kallang Way, with back-end and manufacturing activity.
Website (opens Infineon (Singapore) in a new tab)
ASE Singapore
The Singapore site, at Woodlands, of ASE — the world's largest OSAT group. Provides back-end packaging, wafer-level packaging, final test, wafer sort, product engineering and logistics, with a stated focus on connectivity and automotive markets.
Website (opens ASE Singapore in a new tab)
Silicon Box
An advanced-packaging entrant running a fab at Tampines dedicated to panel-level packaging (PLP) and chiplet interconnection with sub-5-micron fabrication, aimed at AI and high-performance computing. Reported to have shipped over 100 million units — a new entrant already in volume.
Website (opens Silicon Box in a new tab)

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